Progress report L2STT April 2000
  - VIPA crates received from Rittal, shipped to Fermilab for testing by PREP
  - started detailed engineering design of FRC components, particularly issues
    related to PCI interface
  - continued studies of the effects of L1CTT track list truncation
  - began work on a mechanical/electrical test board to verify
    the feasibility of connector alignment between the motherboard and
    daughterboards
  - continued design of STT motherboard
  - assembled prototype of link receiver board
  - began testing prototype of link receiver board
  - began design of link transmitter card
  - continued design of STC daughtercard and made progress in 
    definition of data format and understanding of control logic, buffering, 
    and initialization requirements
  - continued development of VHDL code for cluster finder and hitfilter:
      - began to implement code for monitoring and L3 buffering
      - made changes to the algorithms for the cluster finder and the centroid 
         calculation  (store the address of each strip used in a centroid 
	 calculation,  define a cluster as a set of continuous strip numbers, 
	 find the pulse height (dE / dx) of a cluster)
      - fit hitfilter into Altera EPF10K200EQC208-1
  - continued layout of TFC 
  - continued detailed work on "final" LUT-based track fitting algorithm
  - made progress in understanding of monitoring and downloading requirements
    for STT system
  - continued STT simulator debugging (in particular clustering and tracking)
  - began to address issues related to new trigger simulator/emulator framework