STT Progress report 
May 2000
  
 * continued design of STT motherboard schematic
 
 * debugging of LRB (link receiver board) prototype

 * prototype of LTB (link transmitter board) in hand

 * made decision on choice of in-crate CPU

 * made some progress in specifying test setup
    
 * Framework for track truncation studies has been set up. Short term studies 
   will use the MC_EXAM package with hand-coded simulations of the  truncation
   steps and some relevant trigger conditions.

 * the SCL Init sequence using CPU has been specified, and a document is in 
   preparation.

 * continued engineering  design of the FRC daughterboard and BC board.

 * Simple boards to test connector mechanical tolerances  designed. Sent
   out for fabrication on 6/1.   
   
 * continued engineering specification  of STC daughter card, with lots of 
   progress in specifying the control signals for communication between control
   logic, data flow and buffering for L3.
        
 * development of VHDL code for STC continued:
   - did some small modifications of centroid finder 
   - hit filter design has been modified and  is now being fit in the 
     ACEX family of ALTERA. 
   - have new student working on code for L3 buffering   

 * Rebuilt TFC queuing simulation

 * Installed, configured, and tested VHDL to C conversion program
 
 * continued layout of TFC and made progress with programmable logic coding
 
 * lots of effort invested into STT simulator debugging