STT Progress report 
===================
July 2000

general:
* had design meeting on July 28 at Stony Brook;
* finalized specifications of main components and updated documentation;
* have link transmitter and receiver prototypes in hand -- being tested
* are about a month behind schedule in all aspects of project;

FRC:
* continued track truncation studies using the MC_EXAM package.
* Updated documentation for many aspects of the FRC and Buffer
   Controllers (BC) in preparation for the Stony Brook engineering meeting on
   July 28.
* Proposals for final protocols for all data transfers concerning the
   FRC and Buffer Controller presented at the Stony Brook meeting.
* Simple PC boards to test connector mechanical tolerances
   completed. Tolerances are adequate - all connectors seat
   properly. The issue of daughterboard stiffeners remains open,
   however. 
* Preparation for prototypes of the FRC and BC continues. Logic
   diagrams for nearly all components and first pass FPGA code for
   several of them have been completed.

STC:
* Completed engineering specifications for the control logic for STC
* started work on porting parts of channel logic to Xilinx environment.
* All data formats defined and finalized
* FPGA code for the STC channel, consisting of 
        Memory address decoding, Strip reader, Hit filter and L3 buffering 
   has been completed; it fits in three FLEX 10KE (ALTERA) chips.
   It will be tested and debugged using test vectors and then ported to Xilinx
   environment.
   
TFC:
* continued algorithm development, layout and control logic coding  
   
STT simulator:
* continued debugging and code maintenance
* started implementation of different clustering algorithm (the one used in
  firmware)
* implemented STT simulator code in separate platform (lxfsu4), in order to
  have stable version which is not affected by changes due to new releases.