STT Progress report
=================== 
September 2000

* overall, about 3 months behind schedule

* continued design work on all parts of the system 

* motherboard:
   - layout finished, sent to manufacturer
   - expect 1st prototype beginning of November
   - link receivers and transmitters:
       prototypes in hand, being evaluated; 
       will need some modifications (may need larger FPGA)
       
* FRC:
  - Work continued on coding for the FPGAs in the FRC and BC
    daughterboards -- to be finished by end of October.
  - FPGA, FIFO and DPRAM chips were chosen and samples were ordered for
     prototype construction.
  - Finishing touches were put on a note by Tulika Bose describing the
     effects of track truncation in the L1CTT on triggers that include the
     STT.
     
* TFC
    design: 
      - code for 2 out of 3 FPGA's done, 3rd (easiest of the three) soon;
      - expect prototype in December
      - have all parts in hand, including DSP's, memories
    software for the algorithm: 
      - integer version now gives correct impact parameter and 
        phi0 in trigsim C++
	
* STC: 
     - FPGA code for channel logic underwent some modifications;
         modified/finalized L3 and Hits readout procedures; 
     - FPGA code being debugged using testvectors (SMT data and road data)
     - STC FPGA code (stripreader, cluster finder, hitfilter,..) needs three
        Altera Flex10k chips -- too much (not enough room on board);
	 therefore started to investigate possibility of implementing in Altera
	 Apex or Xilinx;
	-- porting of code to Xilinx Foundation software has begun.  
     - work on  look-up tables for hit filter continued; code much improved and
         made faster; implementation into trigger simulator in progress;
     - studies of road widths and pt bins for hit filter continued;
     
* STT simulator:   
     - The old Translation Manager has been integrally replaced by the  
     new SMTLUTtable functions, that access the SMT geometry in the
     correct way. Old code has been turned off, and the cleaned code has 
     been relinked, compiled and run , and consequently committed to the
     CVS repository.
     All multiple dependencies are now eliminated .

   - The LUT tables from CFT to SMT are now created for each module.
     The code that originates the tables has been added to the simulator 
     and committed to CVS. At present the default configuration does not
     enable the creation of such tables. It is planned that a RCP
     parameter will allow to enable that mode.

   -  The inglobation of the STT Simulator into the IOGen Data Flow scheme 
      has started. The STT will provide track information through creation
      of a class object ("L2STTTrack") accessible by all the rest of the
      D0 trigger components in the D0 Simulator.
      The code makes use of the tsim_l1l2 and I/Ogen packages. It is on
      debugging phase at present.

* beam spot monitoring:
     - made progress in defining specifics of information flow, data bases,...