STT progress report -- November 2000
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motherboard:
- We have two motherboard prototypes in hand.
- The FPGA code is written for version 2 of the LRB, we are working on the
  layout.

FRC:
- Qi An finished the FPGA coding for all elements of the FRC and BC. 
- Work began on the layout of the boards and orders were placed for 
  some of the long lead-time components.

STC:
- Design mainly done, but still being fine-tuned.
- Porting of VHDL code to Apex and Xilinx in progress. Apex implementation
  expected to be finished in December.
- Started thinking in more detail about layout of STC prototype card;  this will
  be different from final card -- only two STC channels per board instead of 8,
  due to uncertainty  of final choice of FPGA.
- Are still looking for replacement for Shweta Lolage who is leaving at the end of
  the year.

TFC:
- In the final stages of layout for the TFC.  We expect to send it out for
  prototype production soon.  The delay from Nov. 15 has been to allow
  additional testing of the FPGA's used for the data routing, road assembly
  and output event building.
- Wendy is progressing on the complete integer code for the DSP fitting.
  She's now using the input format we actually expect for the roads and hits
  and has generated the first real look up tables.
  
trigger simulator:
- some problems were fixed and enhancements were added..
  
CTT to STT broadcasting:
- Steve Linn has joined Brian Connolly in development of VHDL code

CPU's for STT crates:
- three MVME2302 modules with VxWorks licences and hardware for ten adapter
  cards received.
- ordered five more MVME2302, and some stuff for test setup using a windfall 
   money shot from FSU 
    (to save money in the MRI budget)