STT progress report -- January 2001 ==================================== motherboard: - continued testing of prototype motherboard - successful initialization of Universe2 chip - ran PCI bus up to 35MHz (33MHz required) - block transfers work (processor <==> local control FPGA) - PCI bridges work (but only single transfers tested so far) - all PCI-MIP sites work - all PMC sites work (but only J1 and J2 connectors tested) - have first versions of software for initialization and data transfer FRC/BC: - The FRC and BC prototypes were submitted for fabrication. We have enough components on hand to make 2 FRCs and 3 BCs. The boards should be back sometime in the week of Feb. 12. - Work has begun on modifying the PCI device drivers used at BU to test the Link Receiver Boards for use with the FRC and BC. The goal is to be able to do the first acceptance tests on the prototypes independent of the motherboard by simply plugging them into a PCI slot on our PC. An adapter card was ordered to enable us to perform these tests. STC: - finished design of STC prototype, pre-layout in progress; pin-out being checked; - will go out for lay-out and board production soon. - porting of VHDL code from Altera to Xilinx about half done. TFC: - Board layout continued -- expected to be finished by end of February; - had problems with traces around PCI-B interface -- now solved. - Wendy has completed all of the computational parts of the integer algorithm and demonstrated that it meets the required precision. trigger simulator: - integer track fitting code (identical to the one in the DSP) implemented in simulator - hit filter code now uses LUT, as in firmware - presently released version of STT simulator uses SMT data chunk rather than raw data chunk as required for integration into L1L2simul package; switchover to raw data chunk by end February? downloading, monitoring: - Bill Lee is working on calorimeter downloading, as training for future STT downloading needs.