STT progress February 2001
==========================

FRC:
 * An error in thermal coupling on the FRC and BC board layouts was
   discovered by the fabricator. This was corrected in our layouts
   resulting in a delay of approximately 1 week.
   (boards received 03/08/01)

 * Work continued on adapting the BU PCI device driver to the FRC/BC.

STC: 
 * completed VHDL design for STC 1st prototype.
 * continued schematics and layout design of 1st prototype.
 * continued VHDL design for STC 2nd prototype (port to Xilinx)
 * ordered components for 1st prototype
 
LRB: 
 * continue testing 2nd prototype

motherboard:
 * completed testing 1st prototype
 
TFC:
 * prototype boards were sent to manufacturer (expected back March 16)
 * made progress in understanding DSP innards, as first step towards boot and
   operating system code for the DSP 

infrastructure, crates,..:
 * completed engineering redesign of SVX J3 backplane
 * made first assessment of power requirements of STT
 * completed cable map for fibers from splitters to VTM
 * installed fiber splitters in MCH

STT simulator:
 * IOGen-STT code modified to comply with IOGen requirements and installed in
   tsim_L1L2 package