STT monthly progress report for March 2001
==========================================
motherboard:
  * 1st prototype done and tested, 5 more boards on order, 
    to be finished 5/4/01
  * link receiver: 2nd prototype testing/debugging in progress
  * link transmitter: may need an additional prototype
  * J3 backplane layout done 

FRC/BC:

  * The FRC and BC prototypes boards were received from the fabricator
    (03/08/01). 

  * Boards are slowly being populated with components, testing as we
    go. So far the following have been tested on the FRC:
     o power
     o clock distribution 53 and 33 MHz
     o on-board reset
     o minimal PCI communication

  * Work continues on adapting the BU PCI device driver to the 
    needs of the FRC and BC.

  * Testing of the BC can begin when we have built an interface cable
    that will allow it to be plugged into our PC's PCI bus. This will
    be done in April.

TFC:
  * Wendy is working on the DSP "operating system" code. 
   
  * The prototype boards arrived, and we are slowly populating them
    and  testing as we go.  The dc-to-dc converter blocks for the DSP
    power  have been put on the board (from discrete components) and
    are working.  
    No problems have been found yet.

STC:
  * Apex to Xilinx conversion done -- optimization in progress
  * printed circuit for prototype being made;
    components for 3 prototypes in hand;
    prototype will be ready by end April
    
STTsimul:
  *  IOGen - the stt simulator code has been modified and improved so
     that it becomes a component of the tsim_l1l2 package.  As such, it
     has run successfully on a sample of 500 J/psi events.

  * The output of the STT simulator is now an IOGen Object 
    ("stt_track" ). 

  * A new package ( stt_analyze) , has been created, that is accessed
    by the tsim_l1l2 framework, and produces Ntuples for the IOGen stt
    object. -  The code for this package is in debug phase.

  * The inputs to the stt_simulator are at present: 
    UnpDataChunk for the SMT_FE;  UnpDataChunk for the FT_L1 . The
    first input will stay as it is for the time being. The second input
    FT_L1 needs to be converted to an IOGen Object.