Progress report L2STT April 2000 - VIPA crates received from Rittal, shipped to Fermilab for testing by PREP - started detailed engineering design of FRC components, particularly issues related to PCI interface - continued studies of the effects of L1CTT track list truncation - began work on a mechanical/electrical test board to verify the feasibility of connector alignment between the motherboard and daughterboards - continued design of STT motherboard - assembled prototype of link receiver board - began testing prototype of link receiver board - began design of link transmitter card - continued design of STC daughtercard and made progress in definition of data format and understanding of control logic, buffering, and initialization requirements - continued development of VHDL code for cluster finder and hitfilter: - began to implement code for monitoring and L3 buffering - made changes to the algorithms for the cluster finder and the centroid calculation (store the address of each strip used in a centroid calculation, define a cluster as a set of continuous strip numbers, find the pulse height (dE / dx) of a cluster) - fit hitfilter into Altera EPF10K200EQC208-1 - continued layout of TFC - continued detailed work on "final" LUT-based track fitting algorithm - made progress in understanding of monitoring and downloading requirements for STT system - continued STT simulator debugging (in particular clustering and tracking) - began to address issues related to new trigger simulator/emulator framework STT Progress report May 2000 * continued engineering specification of STC daughter card, with lots of progress in specifying the control signals for communication between control logic, data flow and buffering for L3. * development of VHDL code for STC continued: - did some small modifications of centroid finder - hit filter design has been modified and is now being fit in the ACEX family of ALTERA. - have new student working on code for L3 buffering * Rebuilt TFC queuing simulation * Installed, configured, and tested VHDL to C conversion program * lots of effort invested into STT simulator debugging STT Progress report =================== July 2000 general: * had design meeting on July 28 at Stony Brook; * finalized specifications of main components and updated documentation; * have link transmitter and receiver prototypes in hand -- being tested * are about a month behind schedule in all aspects of project; FRC: * continued track truncation studies using the MC_EXAM package. * Updated documentation for many aspects of the FRC and Buffer Controllers (BC) in preparation for the Stony Brook engineering meeting on July 28. * Proposals for final protocols for all data transfers concerning the FRC and Buffer Controller presented at the Stony Brook meeting. * Simple PC boards to test connector mechanical tolerances completed. Tolerances are adequate - all connectors seat properly. The issue of daughterboard stiffeners remains open, however. * Preparation for prototypes of the FRC and BC continues. Logic diagrams for nearly all components and first pass FPGA code for several of them have been completed. STC: * Completed engineering specifications for the control logic for STC * started work on porting parts of channel logic to Xilinx environment. * All data formats defined and finalized * FPGA code for the STC channel, consisting of Memory address decoding, Strip reader, Hit filter and L3 buffering has been completed; it fits in three FLEX 10KE (ALTERA) chips. It will be tested and debugged using test vectors and then ported to Xilinx environment. TFC: * continued alorithm development, layout and control logic coding STT simulator: * continued debugging and code maintenance * started implementation of different clustering algorithm (the one used in firmware) * implemented STT simulator code in separate platform (lxfsu4), in order to have stable version which is not affected by changes due to new releases. STT Progress report =================== August 2000 * continued design work on all parts of the system * TFC design and algorithm development progressing * TFC layout nearly completed * STC: - continued design of channel logic and work on board layout - started testing of VHDL code with test vectors - started generation of look-up tables for hit filter - reinvestigated road widths and pt bins for hit filter * STT simulator: - continued debugging - implemented second clustering algorithm (the one that is in the VHDL code for the STC cluster finder) - implemented code for generation of test vectors for cluster finder and hitfilter - started preparations to use translation manager * beam spot monitoring: - started serious discussion with on-line group and database people to define STT needs STT Progress report =================== September 2000 * overall, about 3 months behind schedule * continued design work on all parts of the system * motherboard: - layout finished, sent to manufacturer - expect 1st prototype beginning of November - link receivers and transmitters: prototypes in hand, being evaluated; will need some modifications (may need larger FPGA) * FRC: - Work continued on coding for the FPGAs in the FRC and BC daughterboards -- to be finished by end of October. - FPGA, FIFO and DPRAM chips were chosen and samples were ordered for prototype construction. - Finishing touches were put on a note by Tulika Bose describing the effects of track truncation in the L1CTT on triggers that include the STT. * TFC design: - code for 2 out of 3 FPGA's done, 3rd (easiest of the three) soon; - expect prototype in December - have all parts in hand, including DSP's, memories software for the algorithm: - integer version now gives correct impact parameter and phi0 in trigsim C++ * STC: - FPGA code for channel logic underwent some modifications; modified/finalized L3 and Hits readout procedures; - FPGA code being debugged using testvectors (SMT data and road data) - STC FPGA code (stripreader, cluster finder, hitfilter,..) needs three Altera Flex10k chips -- too much (not enough room on board); therefore started to investigate possibility of implementing in Altera Apex or Xilinx Virtex; -- porting of code to Xilinx Foundation software has begun. - work on look-up tables for hit filter continued; code much improved and made faster; implementation into trigger simulator in progress; - studies of road widths and pt bins for hit filter continued; * STT simulator: - The old Translation Manager has been integrally replaced by the new SMTLUTtable functions, that access the SMT geometry in the correct way. Old code has been turned off, and the cleaned code has been relinked, compiled and run , and consequently committed to the CVS repository. All multiple dependencies are now eliminated . - The LUT tables from CFT to SMT are now created for each module. The code that originates the tables has been added to the simulator and committed to CVS. At present the default configuration does not enable the creation of such tables. It is planned that a RCP parameter will allow to enable that mode. - The inglobation of the STT Simulator into the IOGen Data Flow scheme has started. The STT will provide track information through creation of a class object ("L2STTTrack") accessible by all the rest of the D0 trigger components in the D0 Simulator. The code makes use of the tsim_l1l2 and I/Ogen packages. It is on debugging phase at present. * beam spot monitoring: - made progress in defining specifics of information flow, data bases,... STT Progress report =================== October 2000 * went through a complete schedule review; compared to schedule of Dec. 1999, we slipped by 4 months; had originally foreseen 60 days for integration tests after 2nd prototype, starting in Feb 2001, now will have 1st prototype in Feb. -- try to do as much of integration tests with 1st prototypes as possible. * continued design work on all parts of the system * motherboard: - received board for 1st prototype, being assembled; * FRC: - finished conceptual design - coding for the FPGAs in the FRC and BC daughterboards essentially finished (prototype version) * TFC - hardware design: Hardware design progressing, but we had a two week delay because problems coming from Phenix interrupted our work in the electronics shop. Chuck is now back on STT project. - algorithm: Continuing work on integer version of fitting algorithm, with the impactparameter and phi0 terms now working using official hardware addressing scheme and coordinate conversion look up table. * STC: - STC FPGA code (stripreader, cluster finder, hitfilter,..) needs three Altera Flex10k chips -- too much (not enough room on board); therefore started implementing in Altera Apex or Xilinx Virtex; - porting of code to Xilinx Foundation, as well as Altera Quartus software in progress - stripreader now implemented in both Xilinx Foundation and Altera Quartus software, being studied, try to optimize code. - looming problem: Shweta Lolage (main author of FPGA code) is graduating -- will leave end of this year; need replacement for her (note funds for FPGA code development from NSF-MRI will then be exhausted) * beam spot monitoring: - made progress understanding possibilities and limitations of presently foreseen data flow; * in-crate CPU's: - MVME2302 boards, plus additional hardware (e.g. parts for adapter cards) for three crates, as well as softare (VXWorks runtime licences) have been ordered. ---------------------------------------------------- STT progress report -- November 2000 ==================================== motherboard: - We have two motherboard prototypes in hand. - The FPGA code is written for version 2 of the LRB, we are working on the layout. FRC: - Qi An finished the FPGA coding for all elements of the FRC and BC. - Work began on the layout of the boards and orders were placed for some of the long lead-time components. STC: - Design mainly done, but still being fine-tuned. - Porting of VHDL code to Apex and Xilinx in progress. Apex implementation expected to be finished in December. - Started thinking in more detail about layout of STC prototype card; this will be different from final card -- only two STC channels per board instead of 8, due to uncertainty of final choice of FPGA. - Are still looking for replacement for Shweta Lolage who is leaving at the end of the year. TFC: - In the final stages of layout for the TFC. We expect to send it out for prototype production soon. The delay from Nov. 15 has been to allow additional testing of the FPGA's used for the data routing, road assembly and output event building. - Wendy is progressing on the complete integer code for the DSP fitting. She's now using the input format we actually expect for the roads and hits and has generated the first real look up tables. trigger simulator: - some problems were fixed and enhancements were added.. CTT to STT broadcasting: - Steve Linn has joined Brian Connolly in development of VHDL code CPU's for STT crates: - three MVME2302 modules with VxWorks licences and hardware for ten adapter cards received. - ordered five more MVME2302, and some stuff for test setup using a windfall money shot from FSU (to save money in the MRI budget) STT progress report -- December 2000 ==================================== motherboard: - Received 2 prototype boards - tested motherboard prototype. Verified power distribution. Loaded firmware for local control FPGA via Altera byteblaster. Succeeded in configuring UniverseII VME-PCI bridge and accessing devices on PCI bus 3. Ran PCI bus clock at 16 MHz. link receiver board: - Received 2 prototype boards - Started testing motherboard prototype boards FRC: - Qi An has written and simulated the FPGA code for all elements of the FRC and BC. - He has also finished the layouts of the FRC and the BC and is now doing final checks before submission. - We plan to submit the layouts to fabrication early in the 2nd week in January. - We currently imagine making 2 FRC prototypes and 2 BC prototypes. But we'll probably have more boards than these made assuming its not too expensive. STC: - Design essentially done. - progress in converting SMT reader and clustering/centroid code to Xilinx. We can possibly fit all 8 channels into one big Xilinx FPGA. - The entire channel logic for the STC has been compiled into a single APEX EP20K400EBC652-1X; uses about 70% of available logic elements, requires 279 I/O pins. this pinout is to be used in 1st prototype design. - completed control logic - debugging in progress; - pinouts and routing for all FPGAs on the STC boards available; - PCI-1 and 2 FPGA code completed - debugging in progress. - Layout of STC prototype card in progress; - have found replacement for Shweta Lolage who graduated and left at the end of the year (Arvindh Lalam) TFC: - layout for the TFC prototype done. - continued work on improvement of tracking algorithm trigger simulator: - some problems were fixed and enhancements were added. did studies of track multiplicities, number of clusters, hits, .. software: - started addressing issues of software needs for testing, debugging, downloading,... CPU's for STT crates: - have received five more MVME2302. STT progress report -- January 2001 ==================================== motherboard: - continued testing of prototype motherboard - successful initialization of Universe2 chip - ran PCI bus up to 35MHz (33MHz required) - block transfers work (processor <==> local control FPGA) - PCI bridges work (but only single transfers tested so far) - all PCI-MIP sites work - all PMC sites work (but only J1 and J2 connectors tested) - have first versions of software for initialization and data transfer. FRC/BC: - The FRC and BC prototypes were submitted for fabrication. We have enough components on hand to make 2 FRCs and 3 BCs. The boards should be back sometime in the week of Feb. 12. - Work has begun on modifying the PCI device drivers used at BU to test the Link Receiver Boards for use with the FRC and BC. The goal is to be able to do the first acceptance tests on the prototypes independent of the motherboard by simply plugging them into a PCI slot on our PC. An adapter card was ordered to enable us to perform these tests. STC: - finished design of STC prototype, pre-layout in progress; pin-out being checked; - will go out for lay-out and board production soon. - porting of VHDL code from Altera to Xilinx about half done TFC: - Board layout continued -- expected to be finished by end of February; - had problems with traces around PCI-B interface -- now solved. - Wendy has completed all of the computational parts of the integer algorithm and demonstrated that it meets the required precision. trigger simulator: - integer track fitting code (identical to the one in the DSP) implemented in simulator - hit filter code now uses LUT, as in firmware - presently released version of STT simulator uses SMT data chunk rather than raw data chunk as required for integration into L1L2simul package; switchover to raw data chunk by end February? downloading, monitoring: - Bill Lee is working on calorimeter downloading, as training for future STT downloading needs. --------------------------------------------------------------------------- STT progress February 2001 ========================== FRC: * An error in thermal coupling on the FRC and BC board layouts was discovered by the fabricator. This was corrected in our layouts resulting in a delay of approximately 1 week. (boards received 03/08/01) * Work continued on adapting the BU PCI device driver to the FRC/BC. STC: * completed VHDL design for STC 1st prototype. * continued schematics and layout design of 1st prototype. * continued VHDL design for STC 2nd prototype (port to Xilinx) * ordered components for 1st prototype LRB: * continue testing 2nd prototype motherboard: * completed testing 1st prototype TFC: * prototype boards were sent to manufacturer (expected back March 16) * made progress in understanding DSP innards, as first step towards boot and operating system code for the DSP infrastructure, crates,..: * completed engineering redesign of SVX J3 backplane * made first assessment of power requirements of STT * completed cable map for fibers from splitters to VTM * installed fiber splitters in MCH STT simulator: * IOGen-STT code modified to comply with IOGen requirements and installed in tsim_L1L2 package STT monthly progress report for March 2001 ========================================== motherboard: * 1st prototype done and tested, 5 more boards on order, to be finished 5/4/01 * link receiver: 2nd prototype testing/debugging in progress * link transmitter: may need an additional prototype * J3 backplane layout done FRC/BC: * The FRC and BC prototypes boards were received from the fabricator (03/08/01). * Boards are slowly being populated with components, testing as we go. So far the following have been tested on the FRC: o power o clock distribution 53 and 33 MHz o on-board reset o minimal PCI communication * Work continues on adapting the BU PCI device driver to the needs of the FRC and BC. * Testing of the BC can begin when we have built an interface cable that will allow it to be plugged into our PC's PCI bus. This will be done in April. TFC: * Wendy is working on the DSP "operating system" code. * The prototype boards arrived, and we are slowly populating them and testing as we go. The dc-to-dc converter blocks for the DSP power have been put on the board (from discrete components) and are working. No problems have been found yet. STC: * Apex to Xilinx conversion done -- optimization in progress * printed circuit for prototype being made; components for 3 prototypes in hand; prototype will be ready by end April STTsimul: * IOGen - the stt simulator code has been modified and improved so that it becomes a component of the tsim_l1l2 package. As such, it has run successfully on a sample of 500 J/psi events. * The output of the STT simulator is now an IOGen Object ( "stt_track" ). * A new package ( stt_analyze) , has been created, that is accessed by the tsim_l1l2 framework, and produces Ntuples for the IOGen stt object. - The code for this package is in debug phase. * The inputs to the stt_simulator are at present: UnpDataChunk for the SMT_FE; UnpDataChunk for the FT_L1 . The first input will stay as it is for the time being. The second input FT_L1 needs to be converted to an IOGen Object. ------------------------------------------------------------ March 2001 1 - STT Trigger Simulator (STR) --------------------- IOGen - the stt simulator code has been modified and improved so that it becomes a component of the tsim_l1l2 package. As such, it has run successfully on a sample of 500 J/psi events. The output of the stt simulator is now an IOGen Object ( "stt_track" ). An new package ( stt_analyze) , has been created, that is accessed by the tsim_l1l2 framework, and produces Ntuples for the IOGen stt object. - The code for this package is in debug phase. The inputs to the stt_simulator are at present: UnpDataChunk for the SMT_FE; UnpDataChunk for the FT_L1 . The first input will stay as it is at present. The second input FT_L! needs to be converted to an IOGen Object. 2 - STT Trigger emulator (STR, BL) ____________________ Input Test Vectors are created by the simulator to be used as input to the VHDL code in the STC card. SMT Test Vectors provide, in ascii format, the data stream n cable format as it comes to the STC card from the VTM, and are used to test the Clusters and Centroids FPGA inthe Hardware. A specific Seuqncer ID and HDI Id can be selected. FRC Test Vectors provide the stream of CFT tracks reaching STC from the FRC card. ALL trhe cft tracks for a given event are provided, to any selected (Sequencer, HDI) . THis input file will be used to test the Filter FPGA in STC. Samples of Input Test Vectors have been provided to the FSU engineers for them to proceed with tests of the Hardwware code. Work is going on to implement the code that will p[roduce the Output Test Vectors, needed to compare the output from teh VHDL to the Output from the simulator. Will be prodiced: Ouptput Test Vectors for centroids; Output Test Vectors for Hits in Roads. The LUT Tables that map a given position of a track in CFT to the min and max strip in SMT that defines its 'road' have been produced for a chosen SMT module. These tables are downloaded and used bythe Filget FPGA in the STC card. ----------------------------------------------------------- April2001 FRC/BC Progress Report: April, 2001 ------------------------------------- 1) Adapter to allow BC to be plugged into PCI bus of PC designed and built. 2) All registers on FRC tested in single write mode. Hi Horst, For April, continue testing prototype boards. Access via PCI tests currently underway. Wendy has initial code for DSP testing ready to try and is cleaning up tfc code in trigsim. John --------------------- May 2001 I've actually remembered! Testing and debugging the TFC prototype continues. We have accessed the DSP's and loaded and run simple test programs. We have also verified that multiple DSP's can be running simultanesouly without conflict. Wendy is continueing the conversion of the fitting program to C and developing the DSP infrastructure software (a simple version of which has been used as the test program).