STT progress June 2000
======================
 * continued work on motherboard schematic

 * continued testing of LRB/LTB prototypes - successfully 
   transferred a few *10**12 bits w/o errors

 * continued work on track truncation studies using the 
   MC_EXAM package.

 * Preliminary FPGA coding for FRC daughterboard and BC board begun

 * Simple PC boards to test connector mechanical tolerances
   have been received. Final mechanical modifications being 
   made before tests.

 * Finished the first pass engineering specification of
   the STC channel logic.

 * continued engineering specifications of the STC control 
   logic

 * continued work on cable map from sequencer to STT

 * continued development of VHDL code for STC:
    - hit filter design completed;
    - one of the six L3 buffering FIFOs was designed to check 
      functionality according to latest specs
    - code for mapping of downloaded data into memory done
    - Strip reader was modified to be able to read two words 
      at a time so as to match the speed of the data flow  
      from the VTM bus.

 * continued TFC board layout and FPGA coding for TFC logic

 * ordered all of the parts for the TFC prototype boards;
   have been in contact with PC board manufacturers to 
   ensure that we're not doing anything they cannot handle.  
   The part orders have gone out largely because of longish
   DSP lead time -- up to 16 weeks for a large order.  
   We will receive enough to omplete a single board on a 
   shorter time scale.

 * The fiber optic patch cables have already arrived at FNAL.  
   The splitter order is in SB bureaucracy.  Will be released
   on July 15.

 * Debugging of STT simulator continued; correction of bug 
   in Roads package led to substantial improvement of 
   tracking efficiency

 * A new class " L2STT_spy" has ben implemented that can 
   be used as a temporary output of the STT processor, 
   for internal, and external use.

 * implementation of  'emulator' features into the 
   Simulator has started.