STT schedule:
(status 6 October)

motherboard:
 - layout complete, sent to manufacturer last Monday, back mid October
 - expect first prototype to be assembled by 1 November
 - evaluation about one month, revison if necessary;
 - open question: replace Universe2 chip by FPGA?
       (note Universe is 5V chip, may be discontinued);
         (decision by 10/20?)
 - expect final prototype by Feb 2001
 - cost 3k$ prototype, 1.5k$ production boards
 
LRB/LTR (link receivers and transmitters):
 - prototypes in hand, being evaluated;
 - known changes:
     - error correction
     - FIFO expensive -- bigger FPGA including FIFO?
         (requires larger FPGA -- Acex?
	   decision 10/20)
 - cost $540 LRB (of which $360 FIFO)
        $182 LTB
		
FRC:
details about FRC schedule can be found at:
http://www.nevis.columbia.edu/~evans/stt/talks/frc_sched_1000.pdf
	
STC:
 - prototype I:
    - FPGA code for STC channel done
       Altera Flex or Apex? (decide 11/1)
    - FPGA code for control logic 11/1
    - FPGA code for PCI 11/1
    - schematic 12/1
    - layout 1/1/01
    - PCB + assembly 2/1/01
    - evaluation ?
    
 - prototype II
    - Altera or Xilinx?
    - 8 channels in large Xilinx chip?
    
 - cost: 
    at present very uncertain;
     note Xilinx Virtex $1500         	   
	   
 	 
TFC: 
  o Status and schedule

         design is nearing completion.
         prototype order expected           Nov. 14
         prototypes expected back to us     Nov. 30    (minimal assembly)
         TFC standalone tests               Dec.1 - Feb. 28
         system testing                     ???? 
         production order placed            ????
     

  o TFC Budget situation
                                                       Est. Remaining
                                   Budget    Spent        purchases
        Shop (design, etc):         $90k      $22k           $50k
        Prototyping + production:  $290k      $40k          $150k
        Originally Fermilab:         $0k      $43k           ???
        ================================================================
        TOTAL                      $380k     $105k          $200

             We estimate having roughly $75k left.

             The prototyping and production costs are for the TFC 
             daughtercard only and do not include the motherboards
		
		
discussion/notes:
 - overall, we are about three months behind schedule
 - had originally foreseen 60 days for integration tests 
   after 2nd prototype, starting in Feb 2001,
    now will have 1st prototype in Feb.
   -- try to do as much of integration tests with 1st prototypes 
       as possible