APPENDIX - D
MATLAB CODE FOR THE MATLAB MODEL OF THE MAIN DATA PATH
D.1 Main design file

% VHDL design and FPLD implementation of the Silicon Track Card
% Shweta Lolage
% this is the main batch file used to run the whole code 

% the downloaded parameters are written in the download_para.m file


read_downloaded_parameter;
% this file is used to take the data from teh commented downloaded_parameter.m file and 
%write the data stream into down_data.m file where it can be easily accessed by the modules

smt_filter;
% this file takes the downloaded parameters required - cav, dav, lnkrdy, delay, event_no
% it takes VTM data from vtm_data.m
% writes the processed data in binary form in smt_data.m

strip_reader;
% this file takes the downloaded parameters required - seqid , hdiid
% data type gain and offset are still taken from the user
% bad channel data is taken from the bad_chan_mem.m file
% takes data from smt_data.m
% writes the processed data into strip_data.m

cluster_finder;
% this file takes the downloaded parameters required -  two data-threshold values
% takes data from strip_data.m
% writes the processed data into cluster_data.m

centroid_calculator;
% this file takes the downloaded parameters required - three pulse-threshold values
% the cluster-type is taken as input from user
% takes data from cluster_data.m
% writes the calculated centroids into centroid_data.m

hit_filter;
% takes data from roads_data.m, which is road data LUT and centroid_data.m
% writes the processed hits into hits_data.m


D.2 Read downloaded parameter

%This program is used to convert the commented 
%downloaded data into a bit and byte stream 
% which can be read by the modules


clear all
clc

do = [];

fid = fopen ('downloaded_parameter.m','r');
t  = fread(fid);

t1 = size (t);
t2 = t1(1);
y = 1;
mark = 0;

while y <= t2,
   
   if t(y) == 37
    if mark == 0
        mark = 1; 
        y = y + 1;
      else
        mark = 0;
        y = y + 1;
      end
  else
      if mark == 0
         if t(y) == 13 |t(y) ==10 | t(y) = 32
            y = y + 1;
         else
	        do1 = t(y);
   	     do = [do do1];
           y = y + 1;
        end
      else
        y = y + 1;
     end
   end

end

s = size(do);
s1 = s(2);

fid = fopen('down_data.m','w');
cluster = fwrite( fid,do);
            
st = fclose('all');   


D.3 SMT Filter

% VHDL design and FPLD implementation of the Silicon Track Card
% Shweta Lolage
% this the code to realise the SMT data filter


clear all 
clc

smt_out = [];
smt_out_p = [];
end_of_event = 0;
z= [];
error = [];
serr = 0;
event_frc = '00';

fid = fopen('down_data.m','r');
A1 = fread(fid);
o=hex2dec(A1);

st = fclose(fid);

cav = o(1);

dav = o(2);
ndav = not(dav);

lnkrdy = o(3);
nlnkrdy = not(lnkrdy);

disable = o(4);
ndisable = not(disable);

delay = o(5)*16 + o(6);
delay_b = dec2bin(delay,8);

event_in = o(7)*16 + o(8);
event_in_b = dec2bin (event_in, 8);

fid= fopen ('vtm_data.m','r');
x=fid;
A=fread(fid);
y=hex2dec(A);

st = fclose(fid);

kq=size(y);
kqq=kq(1);

for k=1:3:kqq
	error1 = y(k);
   error = [error error1];
   
	z1=y(k+1)*16+y(k+2);   
	z=[z z1];
end


datasi=size(z);
datasize=datasi(2);


% the inputs to this block other than the vtm_data, test_data and test inputs are
% frc_start
% delay_in (8 bit value)
% disable
% cav
% dav
% lnkrdy
% event_in
% smt_error_in 

% Some constants required for comparison to be converted into decimal%
zC0 = hex2dec('C0');
bC0 = dec2bin(zC0,8);

wrreq = 0; 
usmt_out = [];
lsmt_out = [];

enable1 = and (cav,ndisable);
enable2 = and (ndav,nlnkrdy);
enable = and (enable1, enable2);

j = 1;

if enable == 1
  
while j <= datasize,
   end_of_event = 0;
  
   if z(j) == zC0
       serr = and (smt_error_in_u, smt_error_in_l);
       serr1 = dec2bin(serr,1);
       
       smt_out1 = ['1' serr1 bC0 event_frc]; % this is the trailer%
       smt_out1_d = bin2dec (smt_out1);
	    smt_out3 = dec2bin (smt_out1_d,32);

       smt_out = [smt_out smt_out1];
		 smt_out_p = [smt_out_p smt_out3];		       
       end_of_event = 1;
       
       j = j + 1;
       
       if z(j) == zC0
          end_of_event = 1;
	       while j <= datasize
   	       j = j + 1;
      	 end
       end
      
    else
        while delay ~= 0 
          delay = delay - 1;
          frc_start = input ('input the frc_start status');
      	 if frc_start == 1 
             event_frc = input('input the new event_no (in hex)');
             delay = 0;
          end
       end
       event_frc = event_in_b;

		usmt_out = z(j);
	   smt_error_in_u = error(j);
      j = j + 1;
      
      lsmt_out = z(j);
  	   smt_error_in_l = error(j);
      j = j + 1;
      
      busmt_out = dec2bin(usmt_out,8);
      blsmt_out = dec2bin(lsmt_out,8);
      smt_out1 = [smt_error_in_u smt_error_in_l busmt_out blsmt_out];
      smt_out1_d = bin2dec (smt_out1);
      smt_out2 = dec2bin (smt_out1_d,18);
      smt_out3 = dec2bin (smt_out1_d,32);

		smt_out = [smt_out smt_out2];
      smt_out_p = [smt_out_p smt_out3];
      
      wrreq = 1;
	end      
end

end

fid = fopen('smt_data.m','w'); % data is written to a file
databits = fwrite( fid,smt_out);

st = fclose ('all');
disp('SMT_data processed');





D.4 Strip Reader


% VHDL design and FPLD implementation of the Silicon Track Card
% Shweta Lolage
% this the code to realise the Strip reader control

clear all

channel= []; 
data = [];
z=[];
output = [];
y = [];
q = [];
r = [];
m = [];

vstate=['s' 'h' 'c' 'z' 'a' 'v'];

fid = fopen('down_data.m','r');
A2 = fread(fid);
o1= hex2dec(A2);
seqid = o1(9)*16 + o1(10);
hdiid= o1(11)*16 + o1(12);
high_z = o1(66);
low_z = o1(67);
high_stereo = o1(68);
low_stereo = o1(69);
high_axial = o1(70);
low_axial =  o1(71);

st = fclose(fid);


fid = fopen ('bad_chan_mem.m','r');
C = fread(fid);
m = hex2dec(C);
st = fclose(fid);


fid = fopen ('gain_offset.m','r');
C1= fread(fid);
go = hex2dec(C1);
st = fclose (fid);


test = input ('set 1 if test data to be used : ');

if test == 1
   fid= fopen('test_data.m','r');
else
   fid= fopen('smt_data.m','r');
end


B=fread(fid);
p = hex2dec(B);
st = fclose(fid);

datasi=size(p);
datasize=datasi(1);


for k=1:18:datasize
   q1=p(k)*2+ p(k+1);   
   q = [q q1];
   
   r1 = p(k+2)*128 + p(k+3)*64 + p(k+4)*32 + p(k+5)*16 + p(k+6)*8 + p(k+7)*4 + p(k+8)*2 +p(k+9);
   r=[r r1];
   
   r1 = p(k+10)*128 + p(k+11)*64 + p(k+12)*32 + p(k+13)*16 + p(k+14)*8 + p(k+15)*4 + p(k+16)*2 +p(k+17);
   r=[r r1];
end

matsize = size (r);
matrixsize = matsize(2);

errcounter1 = 0; %for the error in the seqid%
errcounter2 = 0; %for the error in the byte of zeros% 
eof=hex2dec('C0');
newdata= 0;
eofdata= 0;

state = vstate(1);
j=1;
n = 1;
while (j<=matrixsize)


switch lower (state)
   
case 's'
	eofdata=0;
   sinter = [r(j)];
   if sinter==seqid
      state=vstate(2);
   else
		errcounter1 = errcounter1 + 1;
      state=vstate(2);
   end
	j=j+1;
   
case 'h'
   eofdata = 0;
   hinter =[r(j)];
   if hinter==hdiid
      state=vstate(3);
      newdata= 1;
   else
  		errcounter1 = errcounter1 + 1;
      state=vstate(3);
   end
   j=j+1;

case 'c'
   cinter=[r(j)];
   eofdata = 0;
   if cinter >=128
      chip=cinter;
      
      chip_no = chip - 128;
      gain_add = chip_no;
      offset_add = chip_no + 32;
      gain = go(gain_add)*16 + go(gain_add + 1);
      offset = go(offset_add)* 16 + go(offset_add + 1);
      
      if chip_no >= low_stereo & chip_no <= high_stereo
         datatype = '01';
      elseif chip_no >= low_axial & chip_no <= high_axial
			datatype = '10';
      elseif chip_no >= low_z & chip_no <= high_z
         datatype = '11';
      end 
     
      state=vstate(4);
   else
      state=vstate(1);
      datata=cinter
   end
	j=j+1;
   
case 'z'
   zinter =[r(j)];
   if zinter==0
      state=vstate(5);
   else
      errcounter2=errcounter2+1;
      state=vstate(1);
   end
   j=j+1;

case 'a'
   ainter =[r(j)];
   eofdata = 0;
   if  ainter<=127
	   channel=ainter;
      state=vstate(6);
		j=j+1;
   else
	   if  ainter==eof
         eofdata=1;
	   newb=dec2bin(newdata,1);
      eofb=dec2bin(eofdata,1);
      chipb=dec2bin(dchip,4);
	   chanb=dec2bin(channel,7);

      j = j + 1;
      
      event = r(j);
      event_b = dec2bin(event,8);
      
      output1 = [datatype newb eofb event_b chipb chanb];
      output1_d = bin2dec(output1);
      output1_b = dec2bin(output1_d,23);
      output = [output output1_b];
      
            
	   state=vstate(1);
	   chan=ainter;
	   j=j+1;
      else
        state=vstate(3);
		  chann=ainter;
		  disp(chann);
		  pause
		end
   end

      
case 'v'
   vinter =[r(j)];
   v_data=vinter;
      
   newb=dec2bin(newdata,1);
   eofb=dec2bin(eofdata,1);
   dchip=chip-128;
   chipb=dec2bin(dchip,4);
   chanb=dec2bin(channel,7);
   
   add_bad_chan = (dchip -1)*128 + channel;
   if m(add_bad_chan) == 0 
      data = v_data*gain + offset;
   else
      data = 0;
   end
   
   datab=dec2bin(data,8);
   
   output1 = [datatype newb eofb datab chipb chanb];
   
   output1_d = bin2dec(output1);
   output1_b = dec2bin(output1_d,23);
   output = [output output1_b];   
   
   state=vstate(5);
   newdata = 0;
   
	j=j+1;
otherwise
   state=vstate(1);
         
end


end

fid = fopen('strip_data.m','w'); 
		% the data is written out in 23-bit word format
datastrip = fwrite( fid,output);

st = fclose('all');

disp('Strip data written in the file');
D.5 Cluster finder

   
% VHDL design and FPLD implementation of the Silicon Track Card
% Shweta Lolage
% this the code to realise the Cluster finding algorithm

clear all

data = [];
chip_address = [];
chan_address = [];
address = [];
data_type = [];
new_data =[];
eof_data =[];
c_data_type = [];

rotate =['f' '1' '2' 'p' 't'];


d1 = 0; d2 = 0; d3 = 0; d4 = 0; d5 = 0;  % data buffers

add1 = 0; add2 = 0; add3 = 0; add4 = 0; add5 = 0; % address buffers

s_data1 = 0; s_data2 =0; % shadow data buffers

s_add1 = 0; s_add2 = 0; % shadow address buffers

out_data = []; 
p_address = 0;


fid = fopen('down_data.m','r');
A1 = fread(fid);
o2 = hex2dec(A1);
st = fclose(fid);


fid= fopen('strip_data.m','r');
C=fread(fid);
m = hex2dec(C);
st = fclose(fid);

datasi=size(m);
datasize=datasi(1);


for k=1:23:datasize
   data_type1=m(k)*2+ m(k+1);
   data_type = [data_type data_type1];
   
   new_data1 = m(k+2);
   new_data = [new_data new_data1];
   
   eof_data1 = m(k+3);
   eof_data = [eof_data eof_data1];
   
   data1 = m(k+4)*128 + m(k+5)*64 + m(k+6)*32 + m(k+7)*16 + m(k+8)*8 + m(k+9)*4 + m(k+10)*2 + m(k+11);
   data =[data data1];

   address1 = m(k+12)*1024 + m(k+13)*512 + m(k+14)*256 + m(k+15)*128 + m(k+16)*64 + m(k+17)*32 + m(k+18)*16 + m(k+19)*8 + m(k+20)*4 + m(k+21)*2 + m(k+22);
	address=[address address1];
   
end


matsize = size (data);
matrixsize = matsize(2);

state = rotate(1);

j = 1;
current_data_type = 0;


while (j <= matrixsize)
   
   add_threshold = (4*data_type(j)) + 13;
   threshold1 = o2(add_threshold)*16 + o2(add_threshold + 1);
   threshold2 = o2(add_threshold + 2)*16 + o2(add_threshold + 3);
   
      neof_data = eof_data(j);
      
      if data_type(j) == current_data_type
         end_cluster_1 = 0;
      else
         end_cluster_1 = 1;
      end
      
      if address(j) == (p_address + 1)
         end_cluster_2 = 0;
      else
         end_cluster_2 = 1;
      end
      
      if data(j) < threshold1
         end_cluster_3 = 1;
      else
         end_cluster_3 = 0;
      end 
      
      end_cluster_12 = or (end_cluster_1, end_cluster_2);
      end_cluster_123 = or (end_cluster_12, end_cluster_3);
      
      condition = or(neof_data,end_cluster_123);
      
 switch lower (state)

   case 'f'
      current_data_type = data_type(j);
      d1 = 0;
      d2 = 0;
      d3 = data(j);
      d4 = 0;
      d5 = 0;
      add1 = 0;
      add2 = 0;
      add3 = address(j);
      add4 = 0;
      add5 = 0;
      
      s_data1 = 0;
      s_data2 = 0;
      s_add1 = 0;
      s_add2 = 0;
      
      p_address = address(j);
      j= j + 1;
      state = rotate(2);
      
  case '1'
     current_data_type = data_type(j);
     if condition == 1
        state = rotate(5);
         j = j -1 ;
     else
        
        if data(j) < d3
           d4 = data(j);
	     	  add4 = address(j);
           p_address = address(j);
       	  j= j + 1;
	        state = rotate(3); % the next state is case '2' = rotate (3)
        else
   	     d1 = d2;
      	  d2 = d3;
	        d3 = data(j);
   	     
      	  add1 = add2;
		     add2 = add3;
      	  add3 = address(j);
           
           p_address = address(j);
	        j= j+ 1;
   	     state = rotate(2);  % this state is case '1' = rotate (2)
        
   	  end
     end
     
  case '2'    
     current_data_type = data_type(j);
     if condition == 1
        state = rotate (5);
        j = j -1 ;
     else
        
        if data(j) < d3
          d5= data(j);
	        add5 = address(j);
        
   	     s_data1= d4;
      	  s_data2 = data(j);
           s_add1 = add4;
        	  s_add2 = address(j);
        
           p_address = address(j);

	        state = rotate (4); % next state is case 'p' = rotate (4)
   	      j= j + 1; 
      else     
	       d1 = d3;
   	    d2 = d4;
      	 d3 = data(j);
	       d4 = 0;
   	    d5 = 0;
        
       	 add1 = add3;
	       add2= add4;
   	    add3 = address(j);
      	 add4 = 0;
	       add5 = 0;
        
        	p_address = address(j);
       	j = j + 1;
	      state = rotate (2);
    
     end
     
   end
   
case 'p'
   current_data_type = data_type(j);
   if condition == 1 
      state = rotate (5);
      j = j -1 ;
   else
      
      if data(j) > d3
         d1 = s_data1;
         d2 = s_data2;
         d3 = data(j);
         d4 = 0;
         d5 = 0;
         
         add1 = s_add1;
         add2 = s_add2;
         add3 = address(j);
         add4 = 0;
         add5 = 0;
         
         p_address = address(j);

         state = rotate(2);
         j= j + 1;
      else
         s_data1 = s_data2;
         s_data2 = data (j);
         
         s_add1 = s_add2;
         s_add2 = address(j);
         p_address = address(j);

         state = rotate(4);
         j = j + 1;
      end
      
   end
   
case 't'
   
   if  d3 > threshold2
	   d1_b = dec2bin(d1,8);
   	d2_b = dec2bin(d2,8);
		d3_b = dec2bin(d3,8);
		d4_b = dec2bin(d4,8);
	   d5_b = dec2bin(d5,8);
      
      if add2 == 0
         temp = add3 - 1;
         add2_b = dec2bin (temp,11);
      else
         add2_b = dec2bin(add2,11);
      end
      
      address_passed_on =add2_b;
    	c_data_type_b = dec2bin(current_data_type,2);
      out_data1 = [ c_data_type_b d1_b d2_b d3_b d4_b d5_b add2_b];
     	out_data = [out_data out_data1];
        
		j = j + 1;
      state = rotate(1);
   else
      state = rotate(1);
   end
end

end

fid = fopen('cluster_data.m','w');
cluster = fwrite( fid,out_data);
            
st = fclose('all');   


disp ('The clusters are found!!!!!');
         
         
      
   

D.6 Centroid Calculator


% VHDL design and FPLD implementation of the Silicon Track Card
% Shweta Lolage
% this the code to realise the Centroid Calculation



clear all

% declarations
d1 = []; d2 = [];d3 = []; d4 = []; d5 = [];

add2 = [];
data_type = [];
ctype = [];

out_to_hit = [];

num = 0; den = 0;

quo = 0.0; quo_i = 0; address = 0.0; centroid = 0.0;

fid = fopen('down_data.m','r');
A1 = fread(fid);
o=hex2dec(A1);
st = fclose(fid);

fid= fopen('cluster_data.m','r');
D=fread(fid);
m = hex2dec(D);
st = fclose(fid);

datasi=size(m);
datasize=datasi(1);


for k=1:53:datasize
   data_type1 = m(k)*2 + m(k +1);
   data_type = [data_type data_type1];
   
   d_1= m(k+2)*128+ m(k+3)*64 +m(k+4)*32 + m(k+5)*16 + m(k+6)*8 + m(k+7)*4 + m(k+8)*2 +m(k+9);
   d1 = [d1 d_1];
   
   d_2= m(k+10)*128+ m(k+11)*64 +m(k+12)*32 + m(k+13)*16 + m(k+14)*8 + m(k+15)*4 + m(k+16)*2 +m(k+17);
   d2 = [d2 d_2];
   
   d_3= m(k+18)*128+ m(k+19)*64 +m(k+20)*32 + m(k+21)*16 + m(k+22)*8 + m(k+23)*4 + m(k+24)*2 +m(k+25);
   d3 = [d3 d_3];
   
   d_4= m(k+26)*128+ m(k+27)*64 +m(k+28)*32 + m(k+29)*16 + m(k+30)*8 + m(k+31)*4 + m(k+32)*2 +m(k+33);
   d4 = [d4 d_4];
   
   d_5= m(k+34)*128+ m(k+35)*64 +m(k+36)*32 + m(k+37)*16 + m(k+38)*8 + m(k+39)*4 + m(k+40)*2 +m(k+41);
   d5 = [d5 d_5];
   
   add_1 = m(k+42)*1024 + m(k+43)*512 + m(k+44)*256 + m(k+45)*128 + m(k+46)*64 + m(k+47)*32 + m(k+48)*16 + m(k+49)*8 + m(k+50)*4 + m(k+51)*2 + m(k+52);
	add2=[add2 add_1];
   
end

clusters = size (d1);
clusterno = clusters(2);

cluster_type = o(65);

j= 1;
while ( j <= clusterno)
   
   add_pulse_threshold = data_type(j)*9 + 29;
	threshold1 = o(add_pulse_threshold)*256 + o(add_pulse_threshold +1)*16 + o(add_pulse_threshold+2);
 	threshold2 = o(add_pulse_threshold+ 3)*256 + o(add_pulse_threshold +4)*16 + o(add_pulse_threshold+5);
   threshold3 = o(add_pulse_threshold+6)*256 + o(add_pulse_threshold +7)*16 + o(add_pulse_threshold+8);
    
   
if cluster_type ==0
   num = d4(j)-d2(j);
   den = d2(j) + d3(j) + d4(j);
   
else
   num = d3(j) - d1(j) + (2*d4(j)) + (3*d5(j));
   den = d1(j) + d2(j) + d3(j) + d4(j) + d5(j);
   
end

total_area = d1(j) + d2(j) + d3(j) + d4(j) + d5(j);

if (total_area < threshold1) 
   pulse_area_d = 0;
elseif (total_area >= threshold1 & total_area<= threshold2)
      pulse_area_d = 1;
elseif (total_area >= threshold2 & total_area<= threshold3)
      pulse_area_d = 2;
elseif (total_area >= threshold3)
      pulse_area_d = 3;
end
   
quo = num / den;

quo_i = quo * 4;
address = add2(j)*4;
centroid = address + quo_i;
centroid_b = dec2bin(centroid,13);

pulse_area_b = dec2bin(pulse_area_d,2);

ctype = dec2bin(data_type(j),2);
out_to_hit1 = [ctype pulse_area_b centroid_b];
out_to_hit = [out_to_hit out_to_hit1];

j= j + 1;

end

fid = fopen('centriods_data.m','w');
centroids = fwrite( fid,out_to_hit);

st = fclose('all');   

disp('The centroids are ready');


D.7 Hit Filter


% VHDL design and FPLD implementation of the Silicon Track Card
% Shweta Lolage
% this the code to realise the hit filter



clear all

centroid_type = []; centroid = []; c_precision_d = [];

pulse_area = [];

upper_road = []; lower_road = [];

hit_out = []; hits = [];


fid= fopen('centriods_data.m','r');
E=fread(fid);
n = hex2dec(E);

cen_size=size(n);
c_size=cen_size(1);


for k=1:17:c_size
   centroid_type1 = n(k)*2 + n(k +1);
   centroid_type = [centroid_type centroid_type1];
   
   pulse_area1 = n(k+2)*2 + n(k+3);
   pulse_area = [pulse_area pulse_area1];
   
   centroid_1= n(k+4)*1024+ n(k+5)*512+ n(k+6)*256 +n(k+7)*128 + n(k+8)*64 + n(k+9)*32 + n(k+10)*16 + n(k+11)*8 +n(k+12)*4 +n(k+13)*2 +n(k+14); 
   centroid = [centroid centroid_1];

	c_precision_d_1 = n(k+15)*2 +n(k+16);
   c_precision_d = [c_precision_d c_precision_d_1];
   
end

centroids = size (centroid);
centroidno = centroids(2);

fid= fopen('roads_data.m','r');
F=fread(fid);
d = hex2dec(F);

road_size=size(d);
road_no =road_size(1);


for l=1:22:road_no
   
   upper_road1= d(l)*1024 + d(l+1)*512 + d(l+2)*256 + d(l+3)*128 + d(l+4)*64 + d(l+5)*32 +d(l+6)*16 +d(l+7)*8 +d(l+8)*4 +d(l+9)*2 +d(l+10);
   upper_road = [upper_road upper_road1];

   lower_road1= d(l+11)*1024 +d(l+12)*512 + d(l+13)*256 + d(l+14)*128 + d(l+15)*64 + d(l+16)*32 +d(l+17)*16 +d(l+18)*8 +d(l+19)*4 +d(l+20)*2 +d(l+21);
   lower_road = [lower_road lower_road1];

end

roads = size (upper_road);
roadno = roads(2);
  
x= 1;
while ( x <= centroidno)
  	y =1;  
   while (y <= roadno)
      
      if upper_road(y) >= centroid(x) 
         c1 = 1;
      else 
         c1 = 0;
      end 
      
		if lower_road(y) <= centroid(x) 
         c2 = 1;
      else 
         c2 = 0;
      end 
      
      hit = and(c1,c2);
      
      if hit == 1
         road_b = dec2bin(y,6);
         pulse_area_b = dec2bin(pulse_area(x),2);
         centroid_b = dec2bin(centroid(x),11);
         c_precision_b = dec2bin(c_precision_d(x),2);
         
         hit_out1 = [road_b pulse_area_b centroid_b c_precision_b];
         hit_out= [hit_out hit_out1];
      end
      
      y = y+1;
   end
   x= x+1;
end

fid = fopen('hits.m','w');
hitbits = fwrite( fid,hit_out);
st = fclose('all');   
disp('The hits are done........');

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